Accuracy problem of a DDS at very low frequencies
Clash Royale CLAN TAG#URR8PPP
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First time in my life I'm using this DDS chip (AD9850) to create sine wave at a desired freq, where I upload the lookup table code and the desired freq. command via a with micro-controller. So my knowledge at the moment very limited.
The thing seems fine so far but the problem is at very low frequencies. At 1Hz and even 0.5Hz seems fine. But I also need down to 0.1Hz.
Here is the output of DDS when I send the number 0.1 to the DDS via the micro controller:
In my code I send the command from PC to micro as string and convert it to double.
But for simplicity and to verify I use this code, and for 0.1Hz I set sendFrequency(0.1) in the loop.
But as you see the period is around 11.5 sec instead of 10 sec for 0.1Hz command.
I hope I could explain the issue well. Is there a way to calibrate or fine-tune this so that I would have more accurate result? Or I should live with the accuracy? Btw where in the data sheet one can refer to such relative uncertainty?
dds
edited Nov 22 at 9:23
manassehkatz
22916
asked Nov 21 at 13:16
user1234
3861025
|
show 1 more comment
up vote
8
down vote
favorite
First time in my life I'm using this DDS chip (AD9850) to create sine wave at a desired freq, where I upload the lookup table code and the desired freq. command via a with micro-controller. So my knowledge at the moment very limited.
The thing seems fine so far but the problem is at very low frequencies. At 1Hz and even 0.5Hz seems fine. But I also need down to 0.1Hz.
Here is the output of DDS when I send the number 0.1 to the DDS via the micro controller:
In my code I send the command from PC to micro as string and convert it to double.
But for simplicity and to verify I use this code, and for 0.1Hz I set sendFrequency(0.1) in the loop.
But as you see the period is around 11.5 sec instead of 10 sec for 0.1Hz command.
I hope I could explain the issue well. Is there a way to calibrate or fine-tune this so that I would have more accurate result? Or I should live with the accuracy? Btw where in the data sheet one can refer to such relative uncertainty?
dds
edited Nov 22 at 9:23
manassehkatz
22916
asked Nov 21 at 13:16
user1234
3861025
1
so, what's the control word you're sending to the DDS chip, and what's the reference clock you're using for the DDS chip? What did you expect to happen, and how far off are these 11.5 s from that? We'll need a lot more knowledge on your system!
– Marcus Müller
Nov 21 at 13:26
@MarcusMüller I use this code softgeniedoc.dk/contents/projects/AD9850_tonegen/AD9850.html just abit modified but the core is the same. I couldnt infer what is the clock being used from the code. I provided the code and the chip what else you need more let me provide.
– user1234
Nov 21 at 13:31
you wired up the chip to a reference clock. You're literally the only one in this world who can tell us what the reference clock is; the circuit is sitting in front of you, not of us!
– Marcus Müller
Nov 21 at 13:37
Oh I see I thought it is fixed or changed by the code. I will measure and come back.
– user1234
Nov 21 at 13:38
It is this module telecnatron.com/modules/ad9850/index.html so it seems 125MHz
– user1234
Nov 21 at 13:40
|
show 1 more comment
up vote
8
down vote
favorite
up vote
8
down vote
favorite
First time in my life I'm using this DDS chip (AD9850) to create sine wave at a desired freq, where I upload the lookup table code and the desired freq. command via a with micro-controller. So my knowledge at the moment very limited.
The thing seems fine so far but the problem is at very low frequencies. At 1Hz and even 0.5Hz seems fine. But I also need down to 0.1Hz.
Here is the output of DDS when I send the number 0.1 to the DDS via the micro controller:
In my code I send the command from PC to micro as string and convert it to double.
But for simplicity and to verify I use this code, and for 0.1Hz I set sendFrequency(0.1) in the loop.
But as you see the period is around 11.5 sec instead of 10 sec for 0.1Hz command.
I hope I could explain the issue well. Is there a way to calibrate or fine-tune this so that I would have more accurate result? Or I should live with the accuracy? Btw where in the data sheet one can refer to such relative uncertainty?
dds
edited Nov 22 at 9:23
manassehkatz
22916
asked Nov 21 at 13:16
user1234
3861025
First time in my life I'm using this DDS chip (AD9850) to create sine wave at a desired freq, where I upload the lookup table code and the desired freq. command via a with micro-controller. So my knowledge at the moment very limited.
The thing seems fine so far but the problem is at very low frequencies. At 1Hz and even 0.5Hz seems fine. But I also need down to 0.1Hz.
Here is the output of DDS when I send the number 0.1 to the DDS via the micro controller:
In my code I send the command from PC to micro as string and convert it to double.
But for simplicity and to verify I use this code, and for 0.1Hz I set sendFrequency(0.1) in the loop.
But as you see the period is around 11.5 sec instead of 10 sec for 0.1Hz command.
I hope I could explain the issue well. Is there a way to calibrate or fine-tune this so that I would have more accurate result? Or I should live with the accuracy? Btw where in the data sheet one can refer to such relative uncertainty?
dds
dds
edited Nov 22 at 9:23
manassehkatz
22916
asked Nov 21 at 13:16
user1234
3861025
edited Nov 22 at 9:23
manassehkatz
22916
asked Nov 21 at 13:16
user1234
3861025
edited Nov 22 at 9:23
manassehkatz
22916
edited Nov 22 at 9:23
manassehkatz
22916
edited Nov 22 at 9:23
manassehkatz
22916
22916
asked Nov 21 at 13:16
user1234
3861025
asked Nov 21 at 13:16
user1234
3861025
asked Nov 21 at 13:16
user1234
3861025
3861025
1
so, what's the control word you're sending to the DDS chip, and what's the reference clock you're using for the DDS chip? What did you expect to happen, and how far off are these 11.5 s from that? We'll need a lot more knowledge on your system!
– Marcus Müller
Nov 21 at 13:26
@MarcusMüller I use this code softgeniedoc.dk/contents/projects/AD9850_tonegen/AD9850.html just abit modified but the core is the same. I couldnt infer what is the clock being used from the code. I provided the code and the chip what else you need more let me provide.
– user1234
Nov 21 at 13:31
you wired up the chip to a reference clock. You're literally the only one in this world who can tell us what the reference clock is; the circuit is sitting in front of you, not of us!
– Marcus Müller
Nov 21 at 13:37
Oh I see I thought it is fixed or changed by the code. I will measure and come back.
– user1234
Nov 21 at 13:38
It is this module telecnatron.com/modules/ad9850/index.html so it seems 125MHz
– user1234
Nov 21 at 13:40
|
show 1 more comment
1
so, what's the control word you're sending to the DDS chip, and what's the reference clock you're using for the DDS chip? What did you expect to happen, and how far off are these 11.5 s from that? We'll need a lot more knowledge on your system!
– Marcus Müller
Nov 21 at 13:26
@MarcusMüller I use this code softgeniedoc.dk/contents/projects/AD9850_tonegen/AD9850.html just abit modified but the core is the same. I couldnt infer what is the clock being used from the code. I provided the code and the chip what else you need more let me provide.
– user1234
Nov 21 at 13:31
you wired up the chip to a reference clock. You're literally the only one in this world who can tell us what the reference clock is; the circuit is sitting in front of you, not of us!
– Marcus Müller
Nov 21 at 13:37
Oh I see I thought it is fixed or changed by the code. I will measure and come back.
– user1234
Nov 21 at 13:38
It is this module telecnatron.com/modules/ad9850/index.html so it seems 125MHz
– user1234
Nov 21 at 13:40
1
1
so, what's the control word you're sending to the DDS chip, and what's the reference clock you're using for the DDS chip? What did you expect to happen, and how far off are these 11.5 s from that? We'll need a lot more knowledge on your system!
– Marcus Müller
Nov 21 at 13:26
so, what's the control word you're sending to the DDS chip, and what's the reference clock you're using for the DDS chip? What did you expect to happen, and how far off are these 11.5 s from that? We'll need a lot more knowledge on your system!
– Marcus Müller
Nov 21 at 13:26
@MarcusMüller I use this code softgeniedoc.dk/contents/projects/AD9850_tonegen/AD9850.html just abit modified but the core is the same. I couldnt infer what is the clock being used from the code. I provided the code and the chip what else you need more let me provide.
– user1234
Nov 21 at 13:31
@MarcusMüller I use this code softgeniedoc.dk/contents/projects/AD9850_tonegen/AD9850.html just abit modified but the core is the same. I couldnt infer what is the clock being used from the code. I provided the code and the chip what else you need more let me provide.
– user1234
Nov 21 at 13:31
you wired up the chip to a reference clock. You're literally the only one in this world who can tell us what the reference clock is; the circuit is sitting in front of you, not of us!
– Marcus Müller
Nov 21 at 13:37
you wired up the chip to a reference clock. You're literally the only one in this world who can tell us what the reference clock is; the circuit is sitting in front of you, not of us!
– Marcus Müller
Nov 21 at 13:37
Oh I see I thought it is fixed or changed by the code. I will measure and come back.
– user1234
Nov 21 at 13:38
Oh I see I thought it is fixed or changed by the code. I will measure and come back.
– user1234
Nov 21 at 13:38
It is this module telecnatron.com/modules/ad9850/index.html so it seems 125MHz
– user1234
Nov 21 at 13:40
It is this module telecnatron.com/modules/ad9850/index.html so it seems 125MHz
– user1234
Nov 21 at 13:40
|
show 1 more comment
2 Answers
2
active
oldest
votes
up vote
9
down vote
accepted
It's not an accuracy thing- it's resolution.
The front of the data sheet specifies tuning resolution of 0.0291Hz with a 125MHz clock.
$0.0291 approx dfrac125times 10^62^32$ Hz (since the phase accumulator is 32 bits)
So that's about 30% of your desired output frequency. That comes from the result of adding the LSB of the tuning word to the phase accumulator at 125MHz- for a given clock frequency, it's inherent to the chip and the number of bits they chose for the phase accumulator and tuning word.
You can try reducing the clock frequency- the minimum is 1MHz so you should be able to improve the resolution by more than two orders of magnitude, to around +/-0.23% at 0.1Hz.
$0.23times 10^-3 approx dfrac1times 10^62^32$ Hz resolution with a 1MHz clock
Unfortunately, other things are going to have to change for optimal performance (especially the output filter- which is typically a 7th order elliptical LC filter on these modules).
If you never need to go above, say, 1Hz, you can simply add an RC filter with a cutoff of, say, 100Hz to the existing output and it will be acceptable for many purposes.
answered Nov 21 at 14:00
Spehro Pefhany
200k4146398
1
Nothing divides the 125MHz from what I can see (other than the DDS itself, of course). You would have to unsolder the oscillator and replace it with a different (lower) frequency module. Or disable it and apply an external clock (it may have an enable input..you can look it up). It's a hardware change.
– Spehro Pefhany
Nov 21 at 14:04
1
It does, of course, but they didn't put enough bits in there for your application. If they had added another 8 bits to the tune word and the phase accumulator you'd be happy (and people who don't need such low frequencies would have to pay slightly more and send more bits to tune the DDS so they wouldn't be as happy).
– Spehro Pefhany
Nov 21 at 14:08
1
Correct. But it does accommodate as low as a 1MHz clock so all is not lost, even for your application. The module output filter (those inductors and capacitors and resistors) will not be appropriate though so the output will tend to be noisy with a much lower clock frequency.
– Spehro Pefhany
Nov 21 at 14:12
1
Nothing to do with pins. But the module clock and output filter is designed for 125MHz fixed.
– Spehro Pefhany
Nov 21 at 14:12
1
@SpehroPefhany -- lower end bench FGs can and do use premade DDS chips. Furthermore, ICs like the AD9106 can perform A/FG style (fixed-rate) arbitrary waveform generation. (The higher end ones would indeed use a FPGA + RAM and a separate DAC, but they're still the same basic thing at heart, just rolling their own implementation :)
– ThreePhaseEel
Nov 22 at 0:29
|
show 10 more comments
up vote
7
down vote
What you're looking for on the datasheet is the frequency tuning resolution. For this chip it is 0.0291 Hz for a 125 MHz reference clock input. Your frequency will be rounded to a multiple of this number. This number is based on the frequency of the clock input of the chip.
For example, 0.1 Hz will be rounded to 0.0873 Hz (0.0291*3). The period for 0.0873 Hz is 11.5 seconds which is what you're seeing.
A lower input clock frequency will give higher accuracy at lower frequencies. So if you wanted better accuracy at lower frequencies then lower the clock frequency.
edited Nov 21 at 15:58
jdv
280212
answered Nov 21 at 13:57
Pangus
995
How do you calculate the output rounded freq.? For example if I send 0.5 to the chip can you show what formula used and what would be the output? So that i can predict for each
– user1234
Nov 21 at 13:59
It rounds down to a multiple of 0.0291. To find closest multiples, divide 0.5 by 0.0291, round down to the nearest whole number and multiply by 0.0291. 0.5/0.0291 = 17.18 which we round to 17. Then 17*0.0291=0.4947. So if you input 0.5Hz you would actually see 0.4947Hz
– Pangus
Nov 21 at 14:09
Oh nice I can even plot the error versus freq. now-
– user1234
Nov 21 at 14:10
@ChrisStratton Oops. yeah you are right. I edited my answer. Thanks
– Pangus
Nov 21 at 14:17
1
You can do frequency modulation and amplitude modulation but I don't think you can change the lookup table on the chip. If you are interested in making arbitrary waveforms then it might be worth looking into a different chip or getting a DAC and trying to create your own DDS
– Pangus
Nov 21 at 14:45
|
show 2 more comments
2 Answers
2
active
oldest
votes
2 Answers
2
active
oldest
votes
active
oldest
votes
active
oldest
votes
up vote
9
down vote
accepted
It's not an accuracy thing- it's resolution.
The front of the data sheet specifies tuning resolution of 0.0291Hz with a 125MHz clock.
$0.0291 approx dfrac125times 10^62^32$ Hz (since the phase accumulator is 32 bits)
So that's about 30% of your desired output frequency. That comes from the result of adding the LSB of the tuning word to the phase accumulator at 125MHz- for a given clock frequency, it's inherent to the chip and the number of bits they chose for the phase accumulator and tuning word.
You can try reducing the clock frequency- the minimum is 1MHz so you should be able to improve the resolution by more than two orders of magnitude, to around +/-0.23% at 0.1Hz.
$0.23times 10^-3 approx dfrac1times 10^62^32$ Hz resolution with a 1MHz clock
Unfortunately, other things are going to have to change for optimal performance (especially the output filter- which is typically a 7th order elliptical LC filter on these modules).
If you never need to go above, say, 1Hz, you can simply add an RC filter with a cutoff of, say, 100Hz to the existing output and it will be acceptable for many purposes.
answered Nov 21 at 14:00
Spehro Pefhany
200k4146398
1
Nothing divides the 125MHz from what I can see (other than the DDS itself, of course). You would have to unsolder the oscillator and replace it with a different (lower) frequency module. Or disable it and apply an external clock (it may have an enable input..you can look it up). It's a hardware change.
– Spehro Pefhany
Nov 21 at 14:04
1
It does, of course, but they didn't put enough bits in there for your application. If they had added another 8 bits to the tune word and the phase accumulator you'd be happy (and people who don't need such low frequencies would have to pay slightly more and send more bits to tune the DDS so they wouldn't be as happy).
– Spehro Pefhany
Nov 21 at 14:08
1
Correct. But it does accommodate as low as a 1MHz clock so all is not lost, even for your application. The module output filter (those inductors and capacitors and resistors) will not be appropriate though so the output will tend to be noisy with a much lower clock frequency.
– Spehro Pefhany
Nov 21 at 14:12
1
Nothing to do with pins. But the module clock and output filter is designed for 125MHz fixed.
– Spehro Pefhany
Nov 21 at 14:12
1
@SpehroPefhany -- lower end bench FGs can and do use premade DDS chips. Furthermore, ICs like the AD9106 can perform A/FG style (fixed-rate) arbitrary waveform generation. (The higher end ones would indeed use a FPGA + RAM and a separate DAC, but they're still the same basic thing at heart, just rolling their own implementation :)
– ThreePhaseEel
Nov 22 at 0:29
|
show 10 more comments
up vote
9
down vote
accepted
It's not an accuracy thing- it's resolution.
The front of the data sheet specifies tuning resolution of 0.0291Hz with a 125MHz clock.
$0.0291 approx dfrac125times 10^62^32$ Hz (since the phase accumulator is 32 bits)
So that's about 30% of your desired output frequency. That comes from the result of adding the LSB of the tuning word to the phase accumulator at 125MHz- for a given clock frequency, it's inherent to the chip and the number of bits they chose for the phase accumulator and tuning word.
You can try reducing the clock frequency- the minimum is 1MHz so you should be able to improve the resolution by more than two orders of magnitude, to around +/-0.23% at 0.1Hz.
$0.23times 10^-3 approx dfrac1times 10^62^32$ Hz resolution with a 1MHz clock
Unfortunately, other things are going to have to change for optimal performance (especially the output filter- which is typically a 7th order elliptical LC filter on these modules).
If you never need to go above, say, 1Hz, you can simply add an RC filter with a cutoff of, say, 100Hz to the existing output and it will be acceptable for many purposes.
answered Nov 21 at 14:00
Spehro Pefhany
200k4146398
1
Nothing divides the 125MHz from what I can see (other than the DDS itself, of course). You would have to unsolder the oscillator and replace it with a different (lower) frequency module. Or disable it and apply an external clock (it may have an enable input..you can look it up). It's a hardware change.
– Spehro Pefhany
Nov 21 at 14:04
1
It does, of course, but they didn't put enough bits in there for your application. If they had added another 8 bits to the tune word and the phase accumulator you'd be happy (and people who don't need such low frequencies would have to pay slightly more and send more bits to tune the DDS so they wouldn't be as happy).
– Spehro Pefhany
Nov 21 at 14:08
1
Correct. But it does accommodate as low as a 1MHz clock so all is not lost, even for your application. The module output filter (those inductors and capacitors and resistors) will not be appropriate though so the output will tend to be noisy with a much lower clock frequency.
– Spehro Pefhany
Nov 21 at 14:12
1
Nothing to do with pins. But the module clock and output filter is designed for 125MHz fixed.
– Spehro Pefhany
Nov 21 at 14:12
1
@SpehroPefhany -- lower end bench FGs can and do use premade DDS chips. Furthermore, ICs like the AD9106 can perform A/FG style (fixed-rate) arbitrary waveform generation. (The higher end ones would indeed use a FPGA + RAM and a separate DAC, but they're still the same basic thing at heart, just rolling their own implementation :)
– ThreePhaseEel
Nov 22 at 0:29
|
show 10 more comments
up vote
9
down vote
accepted
up vote
9
down vote
accepted
It's not an accuracy thing- it's resolution.
The front of the data sheet specifies tuning resolution of 0.0291Hz with a 125MHz clock.
$0.0291 approx dfrac125times 10^62^32$ Hz (since the phase accumulator is 32 bits)
So that's about 30% of your desired output frequency. That comes from the result of adding the LSB of the tuning word to the phase accumulator at 125MHz- for a given clock frequency, it's inherent to the chip and the number of bits they chose for the phase accumulator and tuning word.
You can try reducing the clock frequency- the minimum is 1MHz so you should be able to improve the resolution by more than two orders of magnitude, to around +/-0.23% at 0.1Hz.
$0.23times 10^-3 approx dfrac1times 10^62^32$ Hz resolution with a 1MHz clock
Unfortunately, other things are going to have to change for optimal performance (especially the output filter- which is typically a 7th order elliptical LC filter on these modules).
If you never need to go above, say, 1Hz, you can simply add an RC filter with a cutoff of, say, 100Hz to the existing output and it will be acceptable for many purposes.
answered Nov 21 at 14:00
Spehro Pefhany
200k4146398
It's not an accuracy thing- it's resolution.
The front of the data sheet specifies tuning resolution of 0.0291Hz with a 125MHz clock.
$0.0291 approx dfrac125times 10^62^32$ Hz (since the phase accumulator is 32 bits)
So that's about 30% of your desired output frequency. That comes from the result of adding the LSB of the tuning word to the phase accumulator at 125MHz- for a given clock frequency, it's inherent to the chip and the number of bits they chose for the phase accumulator and tuning word.
You can try reducing the clock frequency- the minimum is 1MHz so you should be able to improve the resolution by more than two orders of magnitude, to around +/-0.23% at 0.1Hz.
$0.23times 10^-3 approx dfrac1times 10^62^32$ Hz resolution with a 1MHz clock
Unfortunately, other things are going to have to change for optimal performance (especially the output filter- which is typically a 7th order elliptical LC filter on these modules).
If you never need to go above, say, 1Hz, you can simply add an RC filter with a cutoff of, say, 100Hz to the existing output and it will be acceptable for many purposes.
answered Nov 21 at 14:00
Spehro Pefhany
200k4146398
edited Nov 21 at 21:54
answered Nov 21 at 14:00
Spehro Pefhany
200k4146398
answered Nov 21 at 14:00
Spehro Pefhany
200k4146398
answered Nov 21 at 14:00
Spehro Pefhany
200k4146398
200k4146398
1
Nothing divides the 125MHz from what I can see (other than the DDS itself, of course). You would have to unsolder the oscillator and replace it with a different (lower) frequency module. Or disable it and apply an external clock (it may have an enable input..you can look it up). It's a hardware change.
– Spehro Pefhany
Nov 21 at 14:04
1
It does, of course, but they didn't put enough bits in there for your application. If they had added another 8 bits to the tune word and the phase accumulator you'd be happy (and people who don't need such low frequencies would have to pay slightly more and send more bits to tune the DDS so they wouldn't be as happy).
– Spehro Pefhany
Nov 21 at 14:08
1
Correct. But it does accommodate as low as a 1MHz clock so all is not lost, even for your application. The module output filter (those inductors and capacitors and resistors) will not be appropriate though so the output will tend to be noisy with a much lower clock frequency.
– Spehro Pefhany
Nov 21 at 14:12
1
Nothing to do with pins. But the module clock and output filter is designed for 125MHz fixed.
– Spehro Pefhany
Nov 21 at 14:12
1
@SpehroPefhany -- lower end bench FGs can and do use premade DDS chips. Furthermore, ICs like the AD9106 can perform A/FG style (fixed-rate) arbitrary waveform generation. (The higher end ones would indeed use a FPGA + RAM and a separate DAC, but they're still the same basic thing at heart, just rolling their own implementation :)
– ThreePhaseEel
Nov 22 at 0:29
|
show 10 more comments
1
Nothing divides the 125MHz from what I can see (other than the DDS itself, of course). You would have to unsolder the oscillator and replace it with a different (lower) frequency module. Or disable it and apply an external clock (it may have an enable input..you can look it up). It's a hardware change.
– Spehro Pefhany
Nov 21 at 14:04
1
It does, of course, but they didn't put enough bits in there for your application. If they had added another 8 bits to the tune word and the phase accumulator you'd be happy (and people who don't need such low frequencies would have to pay slightly more and send more bits to tune the DDS so they wouldn't be as happy).
– Spehro Pefhany
Nov 21 at 14:08
1
Correct. But it does accommodate as low as a 1MHz clock so all is not lost, even for your application. The module output filter (those inductors and capacitors and resistors) will not be appropriate though so the output will tend to be noisy with a much lower clock frequency.
– Spehro Pefhany
Nov 21 at 14:12
1
Nothing to do with pins. But the module clock and output filter is designed for 125MHz fixed.
– Spehro Pefhany
Nov 21 at 14:12
1
@SpehroPefhany -- lower end bench FGs can and do use premade DDS chips. Furthermore, ICs like the AD9106 can perform A/FG style (fixed-rate) arbitrary waveform generation. (The higher end ones would indeed use a FPGA + RAM and a separate DAC, but they're still the same basic thing at heart, just rolling their own implementation :)
– ThreePhaseEel
Nov 22 at 0:29
1
1
Nothing divides the 125MHz from what I can see (other than the DDS itself, of course). You would have to unsolder the oscillator and replace it with a different (lower) frequency module. Or disable it and apply an external clock (it may have an enable input..you can look it up). It's a hardware change.
– Spehro Pefhany
Nov 21 at 14:04
Nothing divides the 125MHz from what I can see (other than the DDS itself, of course). You would have to unsolder the oscillator and replace it with a different (lower) frequency module. Or disable it and apply an external clock (it may have an enable input..you can look it up). It's a hardware change.
– Spehro Pefhany
Nov 21 at 14:04
1
1
It does, of course, but they didn't put enough bits in there for your application. If they had added another 8 bits to the tune word and the phase accumulator you'd be happy (and people who don't need such low frequencies would have to pay slightly more and send more bits to tune the DDS so they wouldn't be as happy).
– Spehro Pefhany
Nov 21 at 14:08
It does, of course, but they didn't put enough bits in there for your application. If they had added another 8 bits to the tune word and the phase accumulator you'd be happy (and people who don't need such low frequencies would have to pay slightly more and send more bits to tune the DDS so they wouldn't be as happy).
– Spehro Pefhany
Nov 21 at 14:08
1
1
Correct. But it does accommodate as low as a 1MHz clock so all is not lost, even for your application. The module output filter (those inductors and capacitors and resistors) will not be appropriate though so the output will tend to be noisy with a much lower clock frequency.
– Spehro Pefhany
Nov 21 at 14:12
Correct. But it does accommodate as low as a 1MHz clock so all is not lost, even for your application. The module output filter (those inductors and capacitors and resistors) will not be appropriate though so the output will tend to be noisy with a much lower clock frequency.
– Spehro Pefhany
Nov 21 at 14:12
1
1
Nothing to do with pins. But the module clock and output filter is designed for 125MHz fixed.
– Spehro Pefhany
Nov 21 at 14:12
Nothing to do with pins. But the module clock and output filter is designed for 125MHz fixed.
– Spehro Pefhany
Nov 21 at 14:12
1
1
@SpehroPefhany -- lower end bench FGs can and do use premade DDS chips. Furthermore, ICs like the AD9106 can perform A/FG style (fixed-rate) arbitrary waveform generation. (The higher end ones would indeed use a FPGA + RAM and a separate DAC, but they're still the same basic thing at heart, just rolling their own implementation :)
– ThreePhaseEel
Nov 22 at 0:29
@SpehroPefhany -- lower end bench FGs can and do use premade DDS chips. Furthermore, ICs like the AD9106 can perform A/FG style (fixed-rate) arbitrary waveform generation. (The higher end ones would indeed use a FPGA + RAM and a separate DAC, but they're still the same basic thing at heart, just rolling their own implementation :)
– ThreePhaseEel
Nov 22 at 0:29
|
show 10 more comments
up vote
7
down vote
What you're looking for on the datasheet is the frequency tuning resolution. For this chip it is 0.0291 Hz for a 125 MHz reference clock input. Your frequency will be rounded to a multiple of this number. This number is based on the frequency of the clock input of the chip.
For example, 0.1 Hz will be rounded to 0.0873 Hz (0.0291*3). The period for 0.0873 Hz is 11.5 seconds which is what you're seeing.
A lower input clock frequency will give higher accuracy at lower frequencies. So if you wanted better accuracy at lower frequencies then lower the clock frequency.
edited Nov 21 at 15:58
jdv
280212
answered Nov 21 at 13:57
Pangus
995
How do you calculate the output rounded freq.? For example if I send 0.5 to the chip can you show what formula used and what would be the output? So that i can predict for each
– user1234
Nov 21 at 13:59
It rounds down to a multiple of 0.0291. To find closest multiples, divide 0.5 by 0.0291, round down to the nearest whole number and multiply by 0.0291. 0.5/0.0291 = 17.18 which we round to 17. Then 17*0.0291=0.4947. So if you input 0.5Hz you would actually see 0.4947Hz
– Pangus
Nov 21 at 14:09
Oh nice I can even plot the error versus freq. now-
– user1234
Nov 21 at 14:10
@ChrisStratton Oops. yeah you are right. I edited my answer. Thanks
– Pangus
Nov 21 at 14:17
1
You can do frequency modulation and amplitude modulation but I don't think you can change the lookup table on the chip. If you are interested in making arbitrary waveforms then it might be worth looking into a different chip or getting a DAC and trying to create your own DDS
– Pangus
Nov 21 at 14:45
|
show 2 more comments
up vote
7
down vote
What you're looking for on the datasheet is the frequency tuning resolution. For this chip it is 0.0291 Hz for a 125 MHz reference clock input. Your frequency will be rounded to a multiple of this number. This number is based on the frequency of the clock input of the chip.
For example, 0.1 Hz will be rounded to 0.0873 Hz (0.0291*3). The period for 0.0873 Hz is 11.5 seconds which is what you're seeing.
A lower input clock frequency will give higher accuracy at lower frequencies. So if you wanted better accuracy at lower frequencies then lower the clock frequency.
edited Nov 21 at 15:58
jdv
280212
answered Nov 21 at 13:57
Pangus
995
How do you calculate the output rounded freq.? For example if I send 0.5 to the chip can you show what formula used and what would be the output? So that i can predict for each
– user1234
Nov 21 at 13:59
It rounds down to a multiple of 0.0291. To find closest multiples, divide 0.5 by 0.0291, round down to the nearest whole number and multiply by 0.0291. 0.5/0.0291 = 17.18 which we round to 17. Then 17*0.0291=0.4947. So if you input 0.5Hz you would actually see 0.4947Hz
– Pangus
Nov 21 at 14:09
Oh nice I can even plot the error versus freq. now-
– user1234
Nov 21 at 14:10
@ChrisStratton Oops. yeah you are right. I edited my answer. Thanks
– Pangus
Nov 21 at 14:17
1
You can do frequency modulation and amplitude modulation but I don't think you can change the lookup table on the chip. If you are interested in making arbitrary waveforms then it might be worth looking into a different chip or getting a DAC and trying to create your own DDS
– Pangus
Nov 21 at 14:45
|
show 2 more comments
up vote
7
down vote
up vote
7
down vote
What you're looking for on the datasheet is the frequency tuning resolution. For this chip it is 0.0291 Hz for a 125 MHz reference clock input. Your frequency will be rounded to a multiple of this number. This number is based on the frequency of the clock input of the chip.
For example, 0.1 Hz will be rounded to 0.0873 Hz (0.0291*3). The period for 0.0873 Hz is 11.5 seconds which is what you're seeing.
A lower input clock frequency will give higher accuracy at lower frequencies. So if you wanted better accuracy at lower frequencies then lower the clock frequency.
edited Nov 21 at 15:58
jdv
280212
answered Nov 21 at 13:57
Pangus
995
What you're looking for on the datasheet is the frequency tuning resolution. For this chip it is 0.0291 Hz for a 125 MHz reference clock input. Your frequency will be rounded to a multiple of this number. This number is based on the frequency of the clock input of the chip.
For example, 0.1 Hz will be rounded to 0.0873 Hz (0.0291*3). The period for 0.0873 Hz is 11.5 seconds which is what you're seeing.
A lower input clock frequency will give higher accuracy at lower frequencies. So if you wanted better accuracy at lower frequencies then lower the clock frequency.
edited Nov 21 at 15:58
jdv
280212
answered Nov 21 at 13:57
Pangus
995
edited Nov 21 at 15:58
jdv
280212
edited Nov 21 at 15:58
jdv
280212
edited Nov 21 at 15:58
jdv
280212
280212
answered Nov 21 at 13:57
Pangus
995
answered Nov 21 at 13:57
Pangus
995
answered Nov 21 at 13:57
Pangus
995
995
How do you calculate the output rounded freq.? For example if I send 0.5 to the chip can you show what formula used and what would be the output? So that i can predict for each
– user1234
Nov 21 at 13:59
It rounds down to a multiple of 0.0291. To find closest multiples, divide 0.5 by 0.0291, round down to the nearest whole number and multiply by 0.0291. 0.5/0.0291 = 17.18 which we round to 17. Then 17*0.0291=0.4947. So if you input 0.5Hz you would actually see 0.4947Hz
– Pangus
Nov 21 at 14:09
Oh nice I can even plot the error versus freq. now-
– user1234
Nov 21 at 14:10
@ChrisStratton Oops. yeah you are right. I edited my answer. Thanks
– Pangus
Nov 21 at 14:17
1
You can do frequency modulation and amplitude modulation but I don't think you can change the lookup table on the chip. If you are interested in making arbitrary waveforms then it might be worth looking into a different chip or getting a DAC and trying to create your own DDS
– Pangus
Nov 21 at 14:45
|
show 2 more comments
How do you calculate the output rounded freq.? For example if I send 0.5 to the chip can you show what formula used and what would be the output? So that i can predict for each
– user1234
Nov 21 at 13:59
It rounds down to a multiple of 0.0291. To find closest multiples, divide 0.5 by 0.0291, round down to the nearest whole number and multiply by 0.0291. 0.5/0.0291 = 17.18 which we round to 17. Then 17*0.0291=0.4947. So if you input 0.5Hz you would actually see 0.4947Hz
– Pangus
Nov 21 at 14:09
Oh nice I can even plot the error versus freq. now-
– user1234
Nov 21 at 14:10
@ChrisStratton Oops. yeah you are right. I edited my answer. Thanks
– Pangus
Nov 21 at 14:17
1
You can do frequency modulation and amplitude modulation but I don't think you can change the lookup table on the chip. If you are interested in making arbitrary waveforms then it might be worth looking into a different chip or getting a DAC and trying to create your own DDS
– Pangus
Nov 21 at 14:45
How do you calculate the output rounded freq.? For example if I send 0.5 to the chip can you show what formula used and what would be the output? So that i can predict for each
– user1234
Nov 21 at 13:59
How do you calculate the output rounded freq.? For example if I send 0.5 to the chip can you show what formula used and what would be the output? So that i can predict for each
– user1234
Nov 21 at 13:59
It rounds down to a multiple of 0.0291. To find closest multiples, divide 0.5 by 0.0291, round down to the nearest whole number and multiply by 0.0291. 0.5/0.0291 = 17.18 which we round to 17. Then 17*0.0291=0.4947. So if you input 0.5Hz you would actually see 0.4947Hz
– Pangus
Nov 21 at 14:09
It rounds down to a multiple of 0.0291. To find closest multiples, divide 0.5 by 0.0291, round down to the nearest whole number and multiply by 0.0291. 0.5/0.0291 = 17.18 which we round to 17. Then 17*0.0291=0.4947. So if you input 0.5Hz you would actually see 0.4947Hz
– Pangus
Nov 21 at 14:09
Oh nice I can even plot the error versus freq. now-
– user1234
Nov 21 at 14:10
Oh nice I can even plot the error versus freq. now-
– user1234
Nov 21 at 14:10
@ChrisStratton Oops. yeah you are right. I edited my answer. Thanks
– Pangus
Nov 21 at 14:17
@ChrisStratton Oops. yeah you are right. I edited my answer. Thanks
– Pangus
Nov 21 at 14:17
1
1
You can do frequency modulation and amplitude modulation but I don't think you can change the lookup table on the chip. If you are interested in making arbitrary waveforms then it might be worth looking into a different chip or getting a DAC and trying to create your own DDS
– Pangus
Nov 21 at 14:45
You can do frequency modulation and amplitude modulation but I don't think you can change the lookup table on the chip. If you are interested in making arbitrary waveforms then it might be worth looking into a different chip or getting a DAC and trying to create your own DDS
– Pangus
Nov 21 at 14:45
|
show 2 more comments
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1
so, what's the control word you're sending to the DDS chip, and what's the reference clock you're using for the DDS chip? What did you expect to happen, and how far off are these 11.5 s from that? We'll need a lot more knowledge on your system!
– Marcus Müller
Nov 21 at 13:26
@MarcusMüller I use this code softgeniedoc.dk/contents/projects/AD9850_tonegen/AD9850.html just abit modified but the core is the same. I couldnt infer what is the clock being used from the code. I provided the code and the chip what else you need more let me provide.
– user1234
Nov 21 at 13:31
you wired up the chip to a reference clock. You're literally the only one in this world who can tell us what the reference clock is; the circuit is sitting in front of you, not of us!
– Marcus Müller
Nov 21 at 13:37
Oh I see I thought it is fixed or changed by the code. I will measure and come back.
– user1234
Nov 21 at 13:38
It is this module telecnatron.com/modules/ad9850/index.html so it seems 125MHz
– user1234
Nov 21 at 13:40