Finite State Machine FSM
Clash Royale CLAN TAG#URR8PPP
up vote
2
down vote
favorite
I understand how to make state diagram and make combinational logic (gates) to get a boolean equation for the next state bits and the output bit,
but what is the function of ROM here ?
verilog shift-register register state-machines rom
asked Oct 3 at 23:30
Aren dg
162
add a comment |Â
up vote
2
down vote
favorite
I understand how to make state diagram and make combinational logic (gates) to get a boolean equation for the next state bits and the output bit,
but what is the function of ROM here ?
verilog shift-register register state-machines rom
asked Oct 3 at 23:30
Aren dg
162
add a comment |Â
up vote
2
down vote
favorite
up vote
2
down vote
favorite
I understand how to make state diagram and make combinational logic (gates) to get a boolean equation for the next state bits and the output bit,
but what is the function of ROM here ?
verilog shift-register register state-machines rom
asked Oct 3 at 23:30
Aren dg
162
I understand how to make state diagram and make combinational logic (gates) to get a boolean equation for the next state bits and the output bit,
but what is the function of ROM here ?
verilog shift-register register state-machines rom
verilog shift-register register state-machines rom
asked Oct 3 at 23:30
Aren dg
162
asked Oct 3 at 23:30
Aren dg
162
asked Oct 3 at 23:30
Aren dg
162
asked Oct 3 at 23:30
Aren dg
162
asked Oct 3 at 23:30
Aren dg
162
162
add a comment |Â
add a comment |Â
2 Answers
2
active
oldest
votes
up vote
11
down vote
accepted
Rom(=Read only memory) is a brute force (=absolutely non-minimized) way to implement a combinatoric circuit. Current state bits and inputs together are address, the data stored into that address contains the next state and possible output bits which both can depend on current state and input bits.
When one builds a state machine using standard parts, he probably appreciates a construction where all logic gates in the state transition & output logic are replaced by a single easily programmable IC.
I would add buffer latches to input and output bits to keep sure that inputs are read and outputs are updated in sync, the output bits should in the rom should be surely settled before they are used.
answered Oct 3 at 23:36
user287001
8,4731416
+1 for solid answer. That latched output was called a "Pipeline". Back in the 1980's we would program 4 eproms so we had 32 bits of control lines in the pipeline. It controls ALU, memory and device IO, conditional jumps, etc.
– Sparky256
Oct 4 at 2:11
add a comment |Â
up vote
5
down vote
This look like a general representation of sequential logic. It could be Read Only Memory: Any boolean function or logic gates combination can be implemented as a look-up table, and look-up tables are equivalent to pages of read-only memory where the inputs are the address and the outputs are the content of the memory.
answered Oct 3 at 23:36
pserra
541211
add a comment |Â
2 Answers
2
active
oldest
votes
2 Answers
2
active
oldest
votes
active
oldest
votes
active
oldest
votes
up vote
11
down vote
accepted
Rom(=Read only memory) is a brute force (=absolutely non-minimized) way to implement a combinatoric circuit. Current state bits and inputs together are address, the data stored into that address contains the next state and possible output bits which both can depend on current state and input bits.
When one builds a state machine using standard parts, he probably appreciates a construction where all logic gates in the state transition & output logic are replaced by a single easily programmable IC.
I would add buffer latches to input and output bits to keep sure that inputs are read and outputs are updated in sync, the output bits should in the rom should be surely settled before they are used.
answered Oct 3 at 23:36
user287001
8,4731416
+1 for solid answer. That latched output was called a "Pipeline". Back in the 1980's we would program 4 eproms so we had 32 bits of control lines in the pipeline. It controls ALU, memory and device IO, conditional jumps, etc.
– Sparky256
Oct 4 at 2:11
add a comment |Â
up vote
11
down vote
accepted
Rom(=Read only memory) is a brute force (=absolutely non-minimized) way to implement a combinatoric circuit. Current state bits and inputs together are address, the data stored into that address contains the next state and possible output bits which both can depend on current state and input bits.
When one builds a state machine using standard parts, he probably appreciates a construction where all logic gates in the state transition & output logic are replaced by a single easily programmable IC.
I would add buffer latches to input and output bits to keep sure that inputs are read and outputs are updated in sync, the output bits should in the rom should be surely settled before they are used.
answered Oct 3 at 23:36
user287001
8,4731416
+1 for solid answer. That latched output was called a "Pipeline". Back in the 1980's we would program 4 eproms so we had 32 bits of control lines in the pipeline. It controls ALU, memory and device IO, conditional jumps, etc.
– Sparky256
Oct 4 at 2:11
add a comment |Â
up vote
11
down vote
accepted
up vote
11
down vote
accepted
Rom(=Read only memory) is a brute force (=absolutely non-minimized) way to implement a combinatoric circuit. Current state bits and inputs together are address, the data stored into that address contains the next state and possible output bits which both can depend on current state and input bits.
When one builds a state machine using standard parts, he probably appreciates a construction where all logic gates in the state transition & output logic are replaced by a single easily programmable IC.
I would add buffer latches to input and output bits to keep sure that inputs are read and outputs are updated in sync, the output bits should in the rom should be surely settled before they are used.
answered Oct 3 at 23:36
user287001
8,4731416
Rom(=Read only memory) is a brute force (=absolutely non-minimized) way to implement a combinatoric circuit. Current state bits and inputs together are address, the data stored into that address contains the next state and possible output bits which both can depend on current state and input bits.
When one builds a state machine using standard parts, he probably appreciates a construction where all logic gates in the state transition & output logic are replaced by a single easily programmable IC.
I would add buffer latches to input and output bits to keep sure that inputs are read and outputs are updated in sync, the output bits should in the rom should be surely settled before they are used.
answered Oct 3 at 23:36
user287001
8,4731416
edited Oct 3 at 23:57
answered Oct 3 at 23:36
user287001
8,4731416
answered Oct 3 at 23:36
user287001
8,4731416
answered Oct 3 at 23:36
user287001
8,4731416
8,4731416
+1 for solid answer. That latched output was called a "Pipeline". Back in the 1980's we would program 4 eproms so we had 32 bits of control lines in the pipeline. It controls ALU, memory and device IO, conditional jumps, etc.
– Sparky256
Oct 4 at 2:11
add a comment |Â
+1 for solid answer. That latched output was called a "Pipeline". Back in the 1980's we would program 4 eproms so we had 32 bits of control lines in the pipeline. It controls ALU, memory and device IO, conditional jumps, etc.
– Sparky256
Oct 4 at 2:11
+1 for solid answer. That latched output was called a "Pipeline". Back in the 1980's we would program 4 eproms so we had 32 bits of control lines in the pipeline. It controls ALU, memory and device IO, conditional jumps, etc.
– Sparky256
Oct 4 at 2:11
+1 for solid answer. That latched output was called a "Pipeline". Back in the 1980's we would program 4 eproms so we had 32 bits of control lines in the pipeline. It controls ALU, memory and device IO, conditional jumps, etc.
– Sparky256
Oct 4 at 2:11
add a comment |Â
up vote
5
down vote
This look like a general representation of sequential logic. It could be Read Only Memory: Any boolean function or logic gates combination can be implemented as a look-up table, and look-up tables are equivalent to pages of read-only memory where the inputs are the address and the outputs are the content of the memory.
answered Oct 3 at 23:36
pserra
541211
add a comment |Â
up vote
5
down vote
This look like a general representation of sequential logic. It could be Read Only Memory: Any boolean function or logic gates combination can be implemented as a look-up table, and look-up tables are equivalent to pages of read-only memory where the inputs are the address and the outputs are the content of the memory.
answered Oct 3 at 23:36
pserra
541211
add a comment |Â
up vote
5
down vote
up vote
5
down vote
This look like a general representation of sequential logic. It could be Read Only Memory: Any boolean function or logic gates combination can be implemented as a look-up table, and look-up tables are equivalent to pages of read-only memory where the inputs are the address and the outputs are the content of the memory.
answered Oct 3 at 23:36
pserra
541211
This look like a general representation of sequential logic. It could be Read Only Memory: Any boolean function or logic gates combination can be implemented as a look-up table, and look-up tables are equivalent to pages of read-only memory where the inputs are the address and the outputs are the content of the memory.
answered Oct 3 at 23:36
pserra
541211
answered Oct 3 at 23:36
pserra
541211
answered Oct 3 at 23:36
pserra
541211
answered Oct 3 at 23:36
pserra
541211
541211
add a comment |Â
add a comment |Â
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