mjhjmtu

This article includes a list of references, but its sources remain unclear because it has insufficient inline citations. Please help to improve this article by introducing more precise citations. (June 2013) (Learn how and when to remove this template message)

Meiko

Type	Private
Industry	Computer hardware
Founded	March 1985
Headquarters	Bristol , UK
Key people	Miles Chesney, Managing Director, David Alden, Finance Director, Gerry Talbot, Founder, Roy Bottomley, Founder, Eric Barton, Founder, James Cownie, Founder
Website	www.meiko.com

Meiko Scientific Ltd. was a British supercomputer company based in Bristol, founded by members of the design team working on the INMOS transputer microprocessor.

History

In 1985, when INMOS management suggested the release of the transputer be delayed, Miles Chesney, David Alden, Eric Barton, Roy Bottomley, James Cownie and Gerry Talbot resigned and formed Meiko (Japanese for "well-engineered") to start work on massively parallel machines based on the processor. Nine weeks later they demonstrated a transputer system based on experimental 16 bit transputers at the SIGGRAPH in San Francisco in July 1985.

In 1986 a system based on 32 bit T414 transputers was launched as the Meiko Computing Surface. By 1990, Meiko had sold more than 300 systems and grown to 125 employees. In 1993, Meiko launched the second-generation Meiko CS-2 system, but Meiko ran into financial difficulties in the mid-1990s. The Meiko technical team and technology was transferred to a joint venture company called Quadrics Supercomputers World Ltd. (QSW), formed by Alenia Spazio of Italy in mid-1996. At Quadrics, the CS-2 interconnect technology was developed into QsNet.

As of 2018, a vestigial Meiko website still exists.^[1]

Computing Surface

The Meiko Computing Surface (sometimes retrospectively referred to as the CS-1) was a massively parallel supercomputer. The system was based on the INMOS transputer microprocessor, later also using SPARC and Intel i860 processors.^[2][3]

The Computing Surface architecture comprised multiple boards containing transputers connected together by their communications links via Meiko-designed link switch chips. A variety of different boards were produced with different transputer variants, RAM capacities and peripherals.

The initial software environments provided for the Computing Surface was OPS (Occam Programming System), Meiko's version of INMOS's D700 Transputer Development System. This was soon superseded by a multi-user version, MultiOPS. Later, Meiko introduced M²VCS (Meiko Multiple Virtual Computing Surfaces), a multi-user resource management system let the processors of a Computing Surface be partitioned into several domains of different sizes. These domains were allocated by M²VCS to individual users, thus allowing several simultaneous users access to their own virtual Computing Surfaces. M²VCS was used in conjunction with either OPS or MeikOS, a Unix-like single-processor operating system.

In 1988, Meiko launched the In-Sun Computing Surface, which repackaged the Computing Surface into VMEbus boards (designated the MK200 series) suitable for installation in larger Sun-3 or Sun-4 systems. The Sun acted as "front-end" host system for managing the transputers, running development tools and providing mass storage. A version of M²VCS running as a SunOS daemon called SVCS (Sun Virtual Computing Surfaces) provided access between the transputer network and the Sun host.

As the performance of the transputer became less competitive towards the end of the 1980s (the follow-on T9000 transputer being beset with delays) Meiko added the ability to supplement the transputers with Intel i860 processors. Each i860 board (MK086 or MK096) contained two i860s with up to 32 MB of RAM each, and two T800s providing inter-processor communication. Sometimes known as the Concerto or simply the i860 Computing Surface, these systems had limited success.

Meiko also produced a SPARC processor board, the MK083, which allowed the integration of the SunOS operating system into the Computing Surface architecture, similarly to the In-Sun Computing Surface. These were usually used as front-end host processors for transputer or i860 Computing Surfaces. SVCS, or an improved version, called simply VCS was used to manage the transputer resources. Computing Surface configurations with multiple MK083 boards were also possible.

A major drawback of the Computing Surface architecture was poor I/O bandwidth for general data shuffling. Although aggregate bandwidth for special case data shuffling could be very high, the general case has very poor performance relative to the compute bandwidth. This made the Meiko Computing Surface uneconomic for many applications.

MeikOS

MeikOS (also written as Meikos or MEiKOS) was a Unix-like transputer operating system developed for the Computing Surface during the late 1980s.

MeikOS was derived from an early version of MINIX, extensively modified for the Computing Surface architecture. Unlike HeliOS, another Unix-like transputer operating system, MeikOS was essentially a single-processor operating system with a distributed filesystem. MeikOS was used in conjunction with the M²VCS (Meiko Multiple Virtual Computing Surfaces) resource management software, which partitioned the processors of a Computing Surface into domains, managed user access to these domains, and provided inter-domain communication.

MeikOS had "diskless" and "fileserver" variants, the former running on the seat processor of an M²VCS domain, providing a command line user interface for a particular user; the latter running on processors with attached SCSI hard disks, providing a remote file service (called SFS, Surface File System) to instances of diskless MeikOS. The two communicated via M²VCS.

MeikOS was made obsolete by the introduction of the In-Sun Computing Surface and the Meiko MK083 SPARC processor board, which allowed SunOS and SVCS (Sun Virtual Computing Surfaces, later developed as VCS) to take over the roles of MeikOS and M²VCS respectively. The last MeikOS release was MeikOS 3.06, in early 1991.

CS-1 Interconnect

This was based on the Transputer link protocol. Meiko developed its own switch silicon on and European Silicon Systems, ES2 Gate Array. This ASIC provided static connectivity and limited dynamic connectivity and was designed by Moray McLaren.

CS-2

The CS-2^[4][5][6] was launched in 1993 and was Meiko's second-generation system architecture, superseding the earlier Computing Surface.

The CS-2 was an all-new modular architecture based around SuperSPARC or hyperSPARC processors^[7] and, optionally, Fujitsu μVP vector processors.^[8] These implemented an instruction set similar to the Fujitsu VP2000 vector supercomputer and had a nominal performance of 200 megaflops on double precision arithmetic and double that on single precision. The SuperSPARC processors ran at 40 MHz initially, later increased to 50 MHz. Subsequently, hyperSPARC processors were introduced at 66, 90 or 100 MHz. The CS-2 was intended to scale up to 1024 processors. The largest CS-2 system built was a 224-processor system^[9] installed at Lawrence Livermore National Laboratory.

The CS-2 ran a customized version of Solaris, initially Solaris 2.1, later 2.3 and 2.5.1.

Elan-Elite Interconnect

The processors in a CS-2 were connected by a Meiko-designed multi-stage packet-switched "fat tree" network implemented in custom silicon.^[10][11][12]

This project, codenamed Elan-Elite, was started in 1990, as a speculative project to compete with the T9000 Transputer from Inmos, which Meiko intended to use as an interconnect technology. The T9000 began to suffer massive delays, such that the internal project became the only viable interconnect choice for the CS-2.

This interconnect comprised two devices, code-named Elan (adapter) and Elite (switch). Each processing element included an Elan chip, a communications co-processor based on the SPARC architecture, accessed via a Sun MBus cache coherent interface and providing two 50MB/s bi-directional links. The Elite chip was an 8-way link crossbar switch, used to form the packet-switched network. The switch had limited adaption based on load and priority.^[13]

Both ASICs were fabbed in CMOS Gate Arrays by GEC Plessey in their Roborough, Plymouth semi-conductor fab in 1993.

After the Meiko technology was acquired by Quadrics, the Elan/Elite interconnect technology was developed into QsNet.

Meiko SPARC FPU

Meiko had hired Fred (Mark) Homewood and Moray McLaren both of whom had been instrumental in the design of the T800. Together, they designed and developed an improved, higher performance FPU core, owned by Meiko. This was initially targeted at the Intel 80387 instruction set. An ongoing legal battle between Intel, AMD and others over the 80387 made it clear this project was a commercial non-starter. A chance discussion between McLaren and Andy Bechtolsheim while visiting Sun Microsystems to discuss licensing Solaris caused Meiko to re-target the design for SPARC. Meiko was able to turn around the core FPU design in a short time and LSI Logic fabbed a device for the SPARCstation 1.

A major difference over the T800 FPU was that it fully implemented the IEEE 754 standard for computer arithmetic. This including all rounding modes, denormalised numbers and square root in hardware without taking any hardware exceptions to complete computation.

A SPARCstation 2 design was also developed together with a combined part targeting the SPARCstation 2 ASIC pinout. LSI fabbed and manufactured the separate FPU L64814, as part of their SparKIT chipset.^[14]

The Meiko design was eventually fully licensed to Sun who went on to use it in the MicroSPARC family of ASICs for a number of generations^[15] in return for a one off payment and full Solaris source license.

References

External links

• Meiko (Survey of High Performance Computing Systems)


• Meiko corporate overview (via Internet Archive)


• E. McIntosh and B. Panzer-Steindel. Parallel Processing at CERN. Presented at HEPiX96 Caspur Rome, October 1996.


• 
  Meiko documentation at bitsavers.org