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The answer to this question is probably process-dependent, but what are the limits of the W/L (gate width/gate length) ratio for MOSFETs?

I don't know what is in the realm of the insane. I saw a design example that ended up with transistors sized at 222/0.4 µm, which is a W/L of 555. That seems extremely high to me, but I have no professional design experience, only academic.

It clearly depends on the application. Such ratios would be rare for digital designs, but they would be quite common for analog ones.

I have done low-noise AVLSI designs with 12 paralleled transistor fingers that add up to a 2280 µm/1.8 µm (that is >2 mm width in a 0.6 µm technology) i.e., W/L = 1266. And I would have gone bigger if size had not been one of the main optimization criteria. Note that these large transistors are actually operating in subthreshold with currents as low as 5 µA, and these transistor sizes were increased 50% from the previous design revision that had yield issues due to popcorn noise.

Even in digital designs you can see this. I vaguely remember an old processor in which the main visual feature was a central set of transistors used to drive the clock throughout the IC.

Transistors that large are not unreasonable, particularly for high-current output pin drivers.

Very wide transistors like this are usually constructed as many parallel fingers. Imagine a "comb" of polysilicon gates...the spaces between the comb fingers are the sources and drains, and they alternate so that a single source or drain is shared by two gate fingers. This reduces the effective capacitance of the source and drain. The other potential issue is the resistance of very long, narrow structures (whether they are source/drain diffusions or gate poly). Breaking the long transistor into many fingers helps to reduce the maximum resistance of any one of these structures.

To add to other answers, it's very typical to see $fracWL$ values on the order of 20-30k in higher-power analog/RF, where the end application is e.g. a power amplifier. A particular example involves a multi-finger transistor with a total periphery of 10.8mm on a 0.4$mu m$ process, which comes out to $fracWL = 27000$.

The limits to reasonable/unreasonable are very dependent on the process and end-application. In the space of RF power transistors, typically the geometry of the die will limit the total number of fingers (packaging, handling, and mechanical stress constraints put practical limits on the aspect ratio of die). In addition, at RF frequencies, the phasing of the signal entering the transistor will also limit the effectiveness of a transistor with a very large aspect ratio. This will in turn put an effective upper limit on $fracWL$, but since the length is process dependent, so is this limit.

You'll find switching regulators with onchip MOSFET switching devices, designed to switch amps, over process and temperature and VDD variations. Even 10,000:1 width/length is used for such purposes. Of course the gate capacitance has become huge.

Regarding the opposite, using the channel as a resistor, or as part of a matched pair for linear voltage-to-current converters in a phase-locked-detector, I've used 1:200 (width/length).