mjhjmtu

I'm working on a PCB that allows me to attach a TSSOP IO expander to a breadboard more easily for experimenting. I asked a question regarding the configuration of decoupling capacitors for an IC with 2 supply pins.

One of the recommendations was to add ground pours to the top and bottom layers of the PCB to create low impedance ground connections for the decoupling capacitors and to tie the top and bottom layers with several stitching vias.

How do I know how many stitching vias to place and how do I know where to place them?

Here is what the board looks like so far:

Edit:

Because I'm new to electrical engineering (I'm barely at hobbyist level), it really helps me to see solutions visually. For folks finding this in the future, here's what my latest state is:

If you flip C2 and C3 around this could be a 1-layer board. Flipping them, would also reduce parasitic inductances due to the required vias.

But, to answer your question, for your (low-frequency) application, stitching vias serve just one purpose, to reduce the impedance for any current traveling on the planes. That directly implies that areas of the plane that have little or no current, due to being far from the current paths, don’t require any vias.

In your case you only have 4 pads and a pin that conduct current from the plane. You just require vias near those pads and perhaps the pin (vias are much less conductive than the pin itself). Perhaps 4 vias on the capacitors, and 2 near the IC Gnd.

Any additional vias would mostly be cosmetic, it would be hard to tease apart the effects due to reduction in impedance due to the vias from the increase in impedance due to the added holes in the planes.

If this was a high-frequency a application (e.g., >500MHz) vias would be required near the PCB edges, to avoid unintended emissions and you would need to take into account the impedances to the plane underneath signal lines.

Put 4 at each end, and a couple under the body of the chip. I don't know that there is an exact science behind it. I try to get Gnd vias near the Gnd end of the caps too. You could move C3 & C4 up a little to get Gnd vias between them and C2 and C1.

Just make your top gnd and the bottom vss; this way, you don't need any Vias.

Also, why those weird trace directions at the outer traces of the chip (pin 1 and 2 on each header)?

Also, you don't need a via in j1_12 (aka gnd), as pads go through the board and manufactured boards (boards you don't make yourself) have pads connected through the hole.